Instruction Operands
Operand is a term used to describe any object that is capable of being manipulated. There are three basic types of operands: immediate, register, and memory. An immediate operand is an constant value that is encoded as part of the instruction. These are typically used to specify constant arithmetic, logical or offset values. Only source operands can be used as immediate operands. Register operands are contained in general-purpose register. A memory operand specifies a location in memory, which can contains any of the data types. An instruction can specify either the source or destination operand as a memory operand, but not both.
| Type | Example | Equivalent C/C++ Statement |
|---|---|---|
| Immediate | imul ebx,11h |
ebx *= 0x11 |
| Immediate | mov eax,42 |
eax = 42 |
| Immediate | xor dl,55h |
dl ^= 0x55 |
| Immediate | add esi,8 |
esi += 8 |
| Register | mov eax,ebx |
eax = ebx |
| Register | inc ecx |
ecx += 1 |
| Register | mul ebx |
edx:eax = eax * ebx |
| Memory | mov eax,[ebx] |
eax = *ebx |
| Memory | add eax,[val1] |
eax += *val1 |
| Memory | sub byte[edi],12 |
*(short *)edi -= 12 |
| Memory | or ecx,[ebx+esi] |
ecx |= *(ebx + esi) |
The multiplicative product’s high-order and low-order doublewords are stored in EDX and EAX, respectively.
| Access Memory | Allocate Memory |
|---|---|
byte[ptr] |
db (1 byte) |
word[ptr] |
dw (2 bytes) |
dword[ptr] |
dd (4 bytes) |
qword[ptr] |
dq (8 bytes) |
Memory Addressing Modes
The x86-32 instruction set supports using up to four separate components to specify a memory operand. The four components are a fixed displacement value, a base register, an index register, and a scale factor. An effective address is calculated as follows:
Effective Address = BaseReg + IndexReg * ScaleFactor + Disp
The base register (BaseReg) can be any general-purpose register; the index register (IndexReg) can be any general-purpose register except ESP; Displacement values (Disp) are constant offsets that are encoded within the instruction; valid scale factors (ScaleFactor) include 1,2,4, and 8. The size of the final effective address (EffectiveAddress) is always 32 bits.
| Addressing Form | Example |
|---|---|
| Disp | mov eax,[MyVal] |
| BaseReg | mov eax,[ebx] |
| BaseReg + Disp | mov eax,[ebx+12] |
| Disp + IndexReg * ScaleFactor | mov eax,[MyArray+esi*4] |
| BaseReg + IndexReg | mov eax,[ebx+esi] |
| BaseReg + IndexReg + Disp | mov eax,[ebx+esi+12] |
| BaseReg + IndexReg * ScaleFactor | mov eax,[ebx+esi*4] |
| Basereg + IndexReg * Scalefactor + Disp | mov eax, [ebx+esi*4+20] |
